The interesting thing about Groq has never been that it built an AI chip. Plenty of companies have. The interesting thing is the bet underneath the chip: that the most valuable property in AI inference is not peak throughput but predictability — knowing, to the cycle, exactly when an answer comes back. On June 16, 2026, the U.S. Patent and Trademark Office issued Groq a grant that quietly extends that bet from inside a single die to the way multiple dies are physically stacked together. For anyone sizing the inference-hardware market against NVIDIA, the grant itself matters less than what it reveals about the footprint around it.

The hero patent is US12660683B1, “Tile structures for multiple die tensor streaming processors.” Strip the language down and it describes a way to connect a first die and a second die face-to-face, deliberately offset from each other, and then tile that pairing into an array. In plain market terms: a chiplet packaging method purpose-built for Groq's architecture. This is the same multi-die direction NVIDIA, AMD, and every advanced-packaging roadmap at TSMC have converged on — when you can't make a single die bigger, you bolt dies together. The difference is what Groq is stacking. It is not stacking general-purpose GPU dies; it is stacking its Tensor Streaming Processor, a design whose entire value proposition depends on deterministic scheduling.

The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension forming an offset alignment between the first die and the second die.— Tile structures for multiple die tensor streaming processors, US12660683B1

What the footprint actually protects

A single grant is a fact; a footprint is a strategy. And Groq's footprint reads as a coherent, multi-year build-out of one architectural idea rather than a scattershot patent pile. Start at the core: US12271339B2 covers the instruction format and instruction set architecture for the tensor streaming processor — the ISA itself, organized into “tiles” and “functional slices.” US12411762B2 covers the memory design that splits the processor into memory slices and arithmetic slices. US12340300B1 protects the physical placement of those tiles so data sits close to the units that compute on it. Three grants, one idea: keep everything spatially organized and statically scheduled so the hardware never has to guess.

That static-scheduling philosophy is the whole game, and it is why the rest of the cluster fits together. US12561279B2, issued in February 2026, covers deterministic memory for the streaming processor — a global address space designed so memory access timing is known in advance, not arbitrated at runtime the way a GPU's caches are. US12547459B1 covers the data-transformation algorithms that stream blocks of input data along a “superlane” into the functional slices. And US12277444B2 extends determinism to the network level: a software-defined multiprocessor where nodes establish a “global counter” so that even communication between chips is deterministic. Put the new packaging grant on top of that and the line is clean — Groq now holds protected territory from the single tile, to the die, to the multi-die package, to the multi-node network. The June 16 grant fills the one gap that mattered for scaling: how to get past the single-die ceiling without surrendering the determinism that justifies the whole design.

How the footprint relates to NVIDIA

NVIDIA's position in AI is built on training and on its CUDA software ecosystem. Inference serving is a separate segment, and it is where the economics are shifting: once a model is trained, the recurring cost is serving tokens, and the metrics that matter are latency, throughput-per-watt, and cost-per-token. A GPU is a marvel of flexible parallelism, but flexibility means runtime arbitration — caches, schedulers, memory controllers all making decisions on the fly, which produces variable, hard-to-guarantee latency. Groq's pitch is the inverse: give up generality and schedule everything at compile time to target a predictable service-level latency. The patent footprint is the legal expression of that pitch. It is not trying to out-CUDA NVIDIA; it is fencing off a different way of building the machine entirely.

What does that fence buy in business terms? Three things. First, freedom to operate: by patenting the deterministic ISA, the memory model, the tile placement, and now the multi-die packaging as an integrated stack, Groq adds issued claims that a fast-follower — including a hyperscaler's in-house silicon team — would have to design around to copy the determinism-first approach. Second, a credible scaling story for capital: the multi-die grant signals to anyone funding the buildout that Groq has a roadmap past the reticle limit, which is exactly the question infrastructure investors ask before committing to a non-incumbent's hardware. Third, negotiating leverage. With 67 grants on record concentrated in one architectural lane, Groq holds a portfolio that is coherent enough to be defensible and specific enough to be licensable — useful whether the endgame is independence, partnership, or acquisition.

The caveats are real and worth stating plainly. Issued claims define what can be blocked, not market share; a patent footprint does not put chips in racks or change demand relative to NVIDIA's installed base and software. Determinism is relevant to some inference workloads and not to others, and the addressable slice of the market where it applies is still being drawn. And advanced packaging capacity — the physical ability to actually manufacture these multi-die tiles at volume — is itself a contested, capacity-constrained resource. But strip the noise away and the signal in this week's grant is straightforward: Groq is not hedging its bet. It is patenting determinism at every level of the stack, and it just closed the one hole that would have capped how far that bet could scale.