When a company's patents issue in a batch and most of them are about the same narrow thing, the cluster is worth reading on its own terms. In the week ending 25 May 2026, International Business Machines (IBM) had dozens of patents issue, and a recognizable subset of them describe one idea from several angles: memory cells engineered not just to store data, but to run the multiply-and-accumulate math that artificial neural networks are built on. A granted claim, unlike a published application, is enforceable coverage — so this set is a map of positions IBM has actually locked in, in a corner of AI hardware that sits apart from the graphics-processor stack that dominates the conversation.

The anchor of the cluster is US12635425B2, a stacked conductive-bridge random access memory (CBRAM) device with an access device stacked in series above it. The grant is explicit about why this matters for AI rather than for ordinary storage:

While neural networks can be implemented at a software level, neural networks implemented in hardware are more efficient.— Stacked conductive bridge random access memory and access devices, US12635425B2

That sentence is the whole business thesis of the cluster in one line. The dominant way to run a neural network today is to move enormous volumes of weights and activations between memory and a separate compute chip — the so-called von Neumann bottleneck, where the data movement, not the arithmetic, burns most of the energy. In-memory and analog compute proposes to do the math where the data already lives, inside the memory array itself, using the physics of the memory cell to perform the weighting. IBM's May grants read as coverage across the materials options for exactly that.

Three memory chemistries, one compute idea

The other devices in the set fill out the menu. US12635426B2 covers a resistive random-access memory (ReRAM) device with a step-height difference between electrode sections — ReRAM being one of the most-studied substrates for analog AI accelerators, because a cell's tunable resistance can directly represent a synaptic weight. US12635419B2 describes a stacked spin-orbit-torque magnetoresistive RAM (SOT-MRAM) structure with bottom and top magnetic-tunnel-junction stacks and a spin-Hall-effect rail — a magnetic alternative aimed at the same role with different endurance and speed tradeoffs. Two of these inventions share inventor Takashi Ando, and the CBRAM and ReRAM grants share Hiroyuki Miyazoe, which is a tell that this is one coordinated research line inside IBM Research, not three unrelated filings that happened to issue the same week.

There is a reason a memory house would pursue all three chemistries rather than betting on one. CBRAM, ReRAM, and SOT-MRAM each trade off the same handful of properties an analog AI accelerator cares about — how precisely a cell's state can be tuned to represent a weight, how many times it can be written before it wears out, how fast it reads, and how much it leaks. None has clearly won. By holding issued claims across the set, IBM is positioned regardless of which substrate the broader industry standardizes on, and the shared inventors signal the bets are being placed from one research program rather than hedged blindly. For a business reader, that is the difference between a scattershot portfolio and a deliberate one.

IBM did not stop at the memory cell. The same week's grants extend up the stack into the supporting hardware and methods. US12634111B2 covers verifying remote execution of machine-learning inference under homomorphic encryption using permutations — a method for catching a cloud provider that tampers with an outsourced inference job while the data stays encrypted. And US12633398B2 applies machine learning to a concrete enterprise problem, training a model to flag radiology exams that may have been cherry-picked. Read together with the memory devices, the picture is a company patenting across the layers it has historically sold into: the device physics, the trusted-execution method for running inference in someone else's data center, and a vertical AI application. That vertical reach matters commercially, because IBM's AI revenue has long depended less on selling raw silicon than on selling the encrypted, regulated, enterprise context in which that silicon runs.

What the coverage buys, and what it doesn't

The business read on a cluster like this is about freedom to operate, not about declaring a winner. Issued claims on stacked CBRAM, ReRAM, and SOT-MRAM structures are positions a competitor working the same analog-compute approaches has to design around or license. That is the practical meaning of coverage: it raises the cost of building a directly comparable in-memory accelerator using the same cell architectures. IBM has a long history of monetizing exactly this kind of foundational hardware estate through licensing as much as through products, and a tight, multi-chemistry set of grants is consistent with building optionality across whichever memory technology the market eventually rewards.

The limits are worth stating as plainly as the coverage. A granted patent is enforceable, but these grants describe device structures and fabrication methods, not a shipping accelerator with disclosed performance — issued coverage is not the same as a product roadmap, and IBM's published commercial AI compute has centered on conventional silicon and its telum and AIU lines rather than on a commercialized analog array. The cherry-picking and homomorphic-inference grants are methods that still depend on deployment to matter. And patent counts in a single week are sensitive to the vagaries of when applications clear the examiner, so the cluster is better read as a snapshot of a sustained research direction than as a sudden push. What the week does show, factually, is that IBM holds issued claims spanning the main analog and in-memory memory technologies that the broader field is betting on as a complement to GPU inference — and that those claims came through as a coordinated set rather than one-offs.

For anyone tracking where AI compute could diversify away from a single architecture, that is the signal in the records: the incumbent with the deepest memory-device history just had a run of grants issue that reads as a claim to ground across all three of the leading non-GPU compute substrates at once.