Published patent applications are a delayed read on where a company spent its research budget roughly 18 months earlier. A single week of Intel's publications, dated April 9, 2026, is therefore not a product roadmap, but it does show where filings were being made. Two clusters dominate, and both attach to the same underlying constraint in AI hardware: moving data costs more energy and time than doing the math, and the gap widens as models grow.

The first cluster is analog in-memory computing. US20260099299A1, "Analog multiply-accumulate unit for multibit in-memory cell computing," describes performing the multiply-accumulate operations at the heart of neural-network math using capacitors inside a memory array, generating an analog result rather than shuttling data to a separate logic block. A companion application, US20260100220A1, covers an "SRAM-based in-memory computing macro using analog computation scheme," building a multiply-accumulate array directly into the structure of a standard SRAM block. Filing on both a capacitor-based MAC and an SRAM-based macro in the same week signals work on more than one route to the same idea: do the arithmetic where the data already lives.

Light in the package

The second cluster is silicon photonics, and it is the larger of the two by record count. Four applications describe packaging optical components into the chip assembly. US20260099015A1 and US20260099001A1 both cover photonic-integrated-circuit packaging architectures; US20260099014A1 describes a "semiconductor package with embedded optical die"; and US20260099012A1 covers hybrid-bonded IC die with topographic surface features for joining photonic and electronic die. The last of these states the goal directly.

Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.— Hybrid-bonded IC die having topographic surface features, US20260099012A1

The common thread across the photonics group is bringing the optical-to-electrical boundary closer to the compute die. In an AI data center, the cost of moving activations and weights between chips and between racks is a recognized limit on how large a training or inference job can scale. Filings that embed optical interconnect into the package are aimed at that boundary. They point to investment in interconnect as a first-class design problem, not an afterthought bolted onto the edge of a board.

Where the two clusters meet

The in-memory and photonics clusters are different engineering bets, but they sit on the same diagnosis. In-memory computing attacks the energy and latency cost of moving data between memory and logic on a single chip. Silicon photonics attacks the same cost between chips and across the system. A third application, US20260099522A1, "Audio and video tokenization for multimodal large language models," rounds out the picture on the software-adjacent side: it describes low-power, continuous tokenization and long-context buffering of audio and video for multimodal LLMs on battery-powered client devices — the same data-movement-and-energy concern, pushed to the edge.

Two graphics-and-imaging applications from the same week — temporally amortized supersampling using a neural network (US20260099895A1) and a noise-sampling technique for texture synthesis (US20260099964A1) — show the breadth of what publishes under a single assignee in a single week, and are a useful reminder that not every AI-adjacent filing belongs to the headline story.

For a business reader, the signal worth holding onto is the direction, attributed to the filings rather than to any claim about competitive standing. Intel's published applications from this week indicate sustained work on the data-movement bottleneck from two angles at once — inside memory and through light in the package. Where chip companies are filing on how data moves, rather than only on how fast it computes, is itself a statement about where the constraint now lives in AI hardware.