Most of the attention Intel (INTC) gets in the AI conversation is about the logic die — the CPU or accelerator core, the process node it is built on. A quieter story sits one layer down, and it is where the bottleneck for AI workloads increasingly lives: the memory that feeds the compute, the way that memory is stacked and cooled, and the packaging that wires a stack of dies together. In the week ending 4 May 2026, Intel had a dense run of patents issue on exactly that substrate. A granted claim is enforceable coverage, not a roadmap promise, so this cluster is a map of positions Intel has locked in around three-dimensional memory and advanced packaging — the physical foundation an accelerator is assembled on.

The cluster's center of gravity is stacked memory with cooling designed into the stack. US12616060B2, on stacked random-access memory devices with refrigeration, sets out the problem and the mechanism in its abstract:

The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.— Stacked random-access memory devices with refrigeration, US12616060B2

Stacking memory vertically buys density and shortens the distance data travels, but it concentrates heat — and heat is what limits how hard a stacked device can run. A claim on moving cold up through the stack via dedicated vias is coverage on the thermal problem that gates the density, which is to say coverage on a constraint that sits directly between AI demand and the silicon that serves it.

A cluster around the third dimension

The rest of the set works the same vertical theme. US12615752B2 covers stacked SRAM cells in vertically adjacent layers sharing a common wordline, coupled to an active-cooling structure — doubling word length for a given cell area, with cooling again built in. US12616012B2 covers stacked memory devices connected layer-to-layer by multilayer continuous vias that carry power and data between the layers, with peripheral control logic separated into its own layer. And US12615762B2 covers three-dimensional DRAM built from vertically aligned semiconductor structures with corresponding vertically aligned capacitors. Read together, these are claims across the spectrum of memory types — SRAM and DRAM — all built upward rather than outward, all confronting the power and heat that the third dimension creates.

The other half of the cluster covers how the dies get assembled into a working part. US12615209B2 covers inter-chiplet routing of transactions across multiple heterogeneous chiplets using hierarchical addressing — the routing fabric that lets a package built from different chiplets behave as one device, which is the design pattern behind modern accelerators. US12616042B2 covers a microelectronic assembly with an anchor layer around a bridge die, and US12616026B2 covers a glass-layer package architecture — both part of the advanced-packaging toolkit for connecting dies at high density. A package is only as fast as the interconnect between its dies, so coverage on bridge dies, glass substrates, and chiplet routing is coverage on the assembly economics of an AI part.

Why the cooling shows up so consistently is worth pausing on, because it explains why this is one cluster rather than two unrelated ones. The reason AI accelerators are memory-bound is that moving data between a far-off memory and the compute costs time and power; stacking the memory close to or atop the logic shortens that path. But the same proximity that helps bandwidth concentrates heat in a small volume, and a stack that overheats has to throttle, erasing the advantage. That is why two of the memory grants — US12616060B2 and US12615752B2 — build the cooling into the memory structure itself rather than treating it as a separate facilities problem. Read alongside the chiplet-routing and bridge-die grants, the week's filings describe a single integrated problem: how to put more memory closer to the compute, wire it together at high density, and keep it cool enough to run — the three constraints that, in practice, set the ceiling on an accelerator's usable performance. Coverage that spans all three is coverage on the integration step, which is the part of the AI hardware stack Intel's foundry strategy is explicitly trying to sell.

What the coverage maps, and the limits

Taken together, the week's grants describe Intel claiming ground on the substrate beneath AI logic: stack the memory (SRAM, DRAM), cool the stack (refrigeration, cold vias, active cooling), and wire the dies together (chiplet routing, bridge dies, glass packaging). For a company whose foundry ambition is to manufacture and package other companies' designs as much as to ship its own, coverage on this layer is aligned with where the business is trying to compete — the packaging and integration step that every accelerator, whoever designs the logic, has to pass through. Issued claims here are positions a rival foundry or packaging house working the same stacked-memory and chiplet techniques would have to design around or license.

The limits are the usual ones for a grant cluster, and worth stating plainly. Enforceable coverage is not a shipping product or a disclosed revenue line — these patents describe device structures and methods, and the records do not say how widely Intel uses each one or what it earns from them. Three-dimensional memory, integrated cooling, and chiplet packaging are intensely worked across the industry, so coverage on a specific structure does not foreclose competing approaches. And patent counts in any single week move with examiner timing, so the cluster is a snapshot of a sustained investment, not a sudden turn. What the week shows as fact is consistent and concrete: in the same seven days, Intel had grants issue across stacked SRAM with refrigeration, stacked SRAM with shared wordlines and active cooling, multilayer-via stacked memory, 3D DRAM, inter-chiplet routing, bridge-die packaging, and glass-substrate packaging — a coordinated footprint on the memory-and-packaging foundation that AI compute is assembled on.