The licensing posture here is internal, not external — and that is the whole strategy. Amazon's granted patent US11347480B2, "Transpose operations using processing element array" (issued 2022-05-31, assigned to Amazon Technologies, Inc.), lists Ron Diamant among the inventors. Diamant's name recurs across Amazon's custom-accelerator work, the silicon family marketed as Trainium and Inferentia. The patent is a piece of plumbing in a chip Amazon built to run AI in its own data centers more cheaply.

What does a processing-element array actually do? It is a grid of small compute units that execute the multiply-accumulate operations neural networks are made of; "transpose operations" handle the data-reshaping that matrix math constantly requires. Get those right in hardware and you avoid expensive shuffling in software. It is unglamorous, and that is exactly why it is a cost story rather than a capability one.

“Provided are integrated circuits and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation.”— U.S. Patent No. 11,347,480 source

The clever part — and the reason this is a cost story — is that the patent transposes a matrix without building any dedicated transpose hardware. Claim 1 describes loading a block of tensor data into the processing element array and then performing "a series of multiplication operations with an identity matrix such that each column of the identity matrix is sequentially multiplied by each column of data elements." Multiplying by an identity matrix is, mathematically, a way to move data: a dependent claim notes the array "generates at most one non-zero value for each multiplication of a column of data elements with a column of the identity matrix," so each cycle relocates exactly one element. The summed products land in column partitions of a results buffer, and those columns are then "mapped to row partitions" of the buffer memory — and that row-versus-column remapping is the transpose. The chip reuses the multiply-accumulate fabric it already has, instead of paying silicon for a one-purpose unit.

The claims lean hard on the compiler, which is the part that makes this practical at scale. The device executes "a set of compiler-generated instructions to transpose the tensor," and the compiler decomposes a large tensor into "multiple blocks of data elements, each block of data elements having a size that corresponds to a size of the state buffer," then into sub-blocks "having dimensions not exceeding dimensions of the systolic array." So a tensor too big for the array is automatically tiled to fit, with the compiler emitting the load, multiply, and remap instructions over two separate data buses — one to load operands, one to "propagate columns of an identity matrix … one column at a time during each processing cycle." This is the kind of hardware-software co-design that only pays off if you own both layers, which a vertically integrated cloud provider does.

The patent also frames the transpose as a step inside larger computation, not a standalone utility — which is where it earns its keep. One claim notes the data elements being transposed can be "intermediate results of computations performed by the systolic array," meaning the chip can reshape its own partial results mid-pipeline without round-tripping them out to memory and back. Avoiding that round trip matters because moving data, not doing math, is often the dominant energy and time cost in accelerator workloads. The independent claims also cover the same method expressed three ways — an integrated-circuit device, a system pairing the accelerator with non-transitory memory, and a computer-implemented compiler method — which is the standard way an assignee fences a technique so a competitor cannot route around it by shifting the work between hardware and the toolchain.

Show me the line item — and you will not find it. Amazon does not disclose a standalone "custom silicon savings" figure; AWS results roll up cloud revenue and the infrastructure cost behind it. The patent estate is the only public evidence of the build-your-own-chip lever, because the financial benefit is embedded in segment margin rather than itemized. That is normal disclosure practice, not evasion.

The business logic is a make-vs-buy calculation at hyperscale. Every accelerator Amazon designs and runs in-house is an accelerator it does not buy at a merchant markup. At AWS volume, even a modest per-unit saving compounds into a meaningful margin difference — which is precisely why the company invests in the IP. The patent proves the investment exists, and shows it reaches into details as fine-grained as avoiding a dedicated transpose unit; it does not, and cannot, disclose the per-unit economics.

Distinguish disclosed from inferred, as always. Disclosed: nothing specific about custom-chip unit costs. Documented in the patent record: a sustained Amazon accelerator-design program with named architects and compiler-driven tensor handling. Inferred, not provable: how much the in-house silicon actually improves AWS AI margins. The documents support the existence of the strategy, not a number for its payoff.

For a markets reader, the takeaway is to treat custom silicon as a margin variable, not a press-release talking point. When a cloud provider's AI revenue grows, the quality of that growth depends partly on whether it runs on chips it buys or chips it builds. Patents like this one are where the build side of Amazon's answer is on the public record — right down to the trick of doing a transpose with nothing but the multiply units it already paid for.