Follow the IP and you find the real chip strategy. The published application US20240220202A1, "Multi-modal systolic array for matrix multiplication," lists inventors including Norman Paul Jouppi, Thomas James Norrie, Andrew Everett Phelps, and Christopher Aaron Clark — the names associated with Google's tensor processing unit program. That is not a coincidental cluster; it is the engineering core of a hyperscaler that chose to build its own AI silicon rather than buy all of it.

What did the 10-K actually say about chips? Less than you would like, and that is the point. Alphabet's annual reports describe investment in "servers, network equipment, and data centers" (Alphabet Form 10-K, FY2024, filed 2025-02-05; FY2025, filed 2026-02-05) without breaking out custom-silicon spend as a line. The disclosure tells you the company is buying and building infrastructure; the patent estate tells you what "building" actually means at the chip level.

“A system and method for matrix multiplication using a systolic array configurable between multiple modes of operation. A systolic processor may receive a data type indicator for the matrix multiplication.”— U.S. Patent Application 2024/0220202 A1 source

Here is why the mechanism matters to the money. A systolic array streams data through a fixed grid of multiply-accumulate cells, reusing each input across many operations so the chip spends its energy on math rather than on moving data around. The word that carries the strategy in this application is "multi-modal." Claim 1 describes an array that is "configurable between a first size M×N and a second size 2M×N," switched by a data-type indicator. For one data type the array loads operands across rows 0 to M−1; for another it splits each element into "first and second element halves" and uses rows 0 through 2M−1. In plain terms, the same silicon physically reconfigures to run wide-and-shallow for one number format and narrow-and-deep for another.

The number formats are spelled out, and they are the heart of the cost argument. A dependent claim defines the first data type as 8-bit integer, 8-bit floating point, or 16-bit floating point, and the second as 4-bit integer. Another claim describes feeding "a vector of elements having shape 1*M" for 16-bit float, "2*M" for 8-bit integer, and "2*2M" for 4-bit integer — meaning the lower the precision, the more numbers the array pushes through per cycle. The payoff is quantified in throughput terms: the array is configured "to produce 2×M 24-bit results per cycle for 8-bit and 4-bit integer inputs, and 1×M 32-bit results per cycle for 8-bit and 16-bit floating point inputs," and a final claim sets M=N=128 with 128×128 operand matrices. Lower precision is cheaper per operation; an array that doubles its effective rows to run 4-bit work is squeezing more useful math out of the same transistors. That is efficiency you can translate directly into cost-per-token.

The claim set is unusually specific about how the cells are wired to make this work, and the specificity is the tell that this is production engineering rather than a sketch. The application describes "one or more 16-bit floating point multiply-add chains," with "two additional 8-bit integer multiply-add chains for every 16-bit floating point multiply-add chain" and "two additional 4-bit multiply-add chains" on top of that, so a single cell can process 8-bit float on the float chain, 8-bit integer on the integer chains, and 4-bit integer by recruiting both. Reusing the same arithmetic hardware across four formats is how you avoid paying silicon area several times over — the area-efficiency move that keeps a custom part cost-competitive with a general-purpose GPU.

The application also handles the messy reality that not every format the array sees is one it natively supports. A claim describes a holding register that can "contain at least one data type that is not supported by the systolic array," converting, for example, 8-bit floating point to 16-bit floating point as data is fed in. Each cell contains both a floating-point dot-product accumulator and multiple integer accumulators, with "separate first and second datapaths" inside the integer units so a single cell can be reused across 8-bit and 4-bit integer work. And claim 13 makes the commercial target explicit: the accelerator hardware unit "is one of a graphics processing unit or a tensor processing unit." This is TPU-class plumbing, described by the people who build TPUs.

The buy-vs-build framing is the business story. Buying merchant accelerators is capex you can scale immediately; building your own is a multi-year IP and engineering bet that pays back only at volume. A patent like this is evidence of the build side of that bet, accumulated over years by the same team, and it shows the build is aimed at precisely the efficiency knobs — reconfigurable precision, format conversion, datapath reuse — that determine whether in-house silicon beats a merchant part. It does not disclose unit costs or volumes; those are not in the filing or the patent.

Distinguish what is disclosed from what is inferred. Disclosed: Alphabet invests heavily in technical infrastructure. Documented in the patent record: a sustained custom-silicon program with named architects and a specific multi-modal array design down to the bit-width. Inferred, and not provable from either source: how much cheaper a TPU is per unit of useful compute than the alternative. The honest read stops at the boundary of the documents.

For an investor reading the AI-capex debate, this is the grounding move. When a hyperscaler's capex rises, ask whether it is buying chips or building them — because the two have very different margin and lock-in implications. The patent estate, not the press release, is where the build half of that answer lives, and this application is a detailed, dated entry in it.