Follow the IP and you find the real chip strategy. The published application US20240220202A1, "Multi-modal systolic array for matrix multiplication," lists inventors including Norman Paul Jouppi, Thomas James Norrie, Andrew Everett Phelps, and Christopher Aaron Clark — the names associated with Google's tensor processing unit program. That is not a coincidental cluster; it is the engineering core of a hyperscaler that chose to build its own AI silicon rather than buy all of it.
What did the 10-K actually say about chips? Less than you would like, and that is the point. Alphabet's annual reports describe investment in "servers, network equipment, and data centers" (Alphabet Form 10-K, FY2024, filed 2025-02-05; FY2025, filed 2026-02-05) without breaking out custom-silicon spend as a line. The disclosure tells you the company is buying and building infrastructure; the patent estate tells you what "building" actually means at the chip level.
Here is why the mechanism matters to the money. A systolic array streams data through a fixed grid of multiply-accumulate cells, reusing each input across many operations so the chip spends its energy on math rather than on moving data around. "Multi-modal" in this application points to an array that flexibly handles the different numeric formats AI workloads demand. Efficiency at this layer is what makes a custom accelerator competitive with a merchant GPU — and competitive enough to justify the design cost.
The buy-vs-build framing is the business story. Buying merchant accelerators is capex you can scale immediately; building your own is a multi-year IP and engineering bet that pays back only at volume. A patent like this is evidence of the build side of that bet, accumulated over years by the same team. It does not disclose unit costs or volumes — those are not in the filing or the patent — but it shows the strategy is real and protected.
Distinguish what is disclosed from what is inferred. Disclosed: Alphabet invests heavily in technical infrastructure. Documented in the patent record: that infrastructure includes a sustained custom-silicon program with named architects and specific array designs. Inferred, and not provable from either source: how much cheaper a TPU is per unit of useful compute than the alternative. The honest read stops at the boundary of the documents.
For an investor reading the AI-capex debate, this is the grounding move. When a hyperscaler's capex rises, ask whether it is buying chips or building them — because the two have very different margin and lock-in implications. The patent estate, not the press release, is where the build half of that answer lives.