What did the market actually reward in AI silicon? Cost-per-useful-compute, more than raw peak numbers. A merchant accelerator wins design slots when it delivers more useful work per dollar and per watt than the alternative — and one of the largest sources of waste in neural-network math is multiplying by zero. Sparsity exploits that.

Intel's granted patent US11204977B2, "Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs" (issued 2021-12-21, assigned to Intel Corporation), is exactly this lever. Neural-network weight matrices are often mostly zeros after pruning; a systolic array that skips those zeros does the same computation with fewer cycles. That is free performance — or, equivalently, lower cost for the same result — and it is the kind of edge a merchant vendor must own to compete.

“Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic…”— U.S. Patent No. 11,204,977 source

The mechanism that turns sparsity from a nice idea into hardware is in the claims, and it is the "feedback inputs" in the title. Claim 1 describes a "pipelined systolic dot product unit" in which a dot product computed at one pipeline stage "is configured to be selectably written via output hardware to a location selected from one of output memory and a second pipeline stage," and a later stage can feed its result back to the first. That feedback path is what lets the unit keep busy: instead of stalling when an operand is zero, the array routes partial results back into the pipeline and packs in the work that actually matters. A systolic array with no feedback marches in lockstep and wastes cycles on zeros; one with feedback can fill those gaps.

The claims also describe how the zeros get found and grouped in the first place. The device includes "hardware circuitry to detect non-zero values within the multiple data elements of the second matrix" and to "group detected non-zero values … into a group" whose size "corresponds with a number of pipeline stages of the systolic processing pipeline." In other words, the hardware scans one operand matrix, pulls out only the entries that are not zero, and bundles exactly as many of them as the pipeline has stages to chew on — then provides "a first data element of the group to the first pipeline stage" and "a second data element to the second pipeline stage." A dependent claim notes the pipeline can be two stages or four; another describes a second, parallel systolic pipeline, and processing elements with "multiple parallel processor channels," each operating "on a vector of multiple data elements." Detection, grouping, feedback, and parallelism together are how the design turns matrix sparsity into fewer real cycles.

The accelerator claims wrap that compute core in the system context a data-center part needs: a host interface, a fabric interconnect, and "one or more hardware tiles" containing a "modular systolic processing array with feedback inputs," built from "multiple processing array modules." Modular and tiled is the language of something meant to scale across a large chip — the "scalable" in the title is structural, not marketing.

Two more details in the claims show how seriously the design treats throughput. First, the processing array modules can run independently: one claim describes "a first pipeline path configurable to execute a first dot product instruction having a first set of inputs and a second pipeline path configurable to execute a second dot product instruction having a second set of inputs." Independent paths mean the hardware does not idle one lane while another works. Second, each path has "separate output hardware for each pipeline stage," so a result can leave the pipeline the moment it is ready rather than waiting to drain the whole array. Every one of these choices — independent paths, per-stage outputs, feedback routing — is aimed at keeping the multiply-accumulate cells busy on non-zero work, which is the entire economic point of a sparse accelerator.

Show me the strategic context. Intel is not the volume leader in AI accelerators, which makes efficiency IP disproportionately important to its competitive case: it has to win on cost-per-compute where it cannot win on installed base or software ecosystem. A sparse-matmul patent is a claim on doing more with less silicon — precisely the argument a challenger makes to a cost-conscious buyer.

The disclosure caveat is real. Intel's filings discuss its data-center and AI ambitions in broad terms, but no 10-K attributes revenue to a specific architectural feature like sparsity. The patent tells you where the engineering edge is being sought; it does not tell you whether it translated into design wins or revenue. Those are separate questions the filing does not answer, and the claims quantify cycles saved only in relative terms — skipping zeros — not in dollars.

Distinguish a held patent from an asserted one, and a method from a market position. This is a granted patent Intel holds; there is no implication here of litigation or licensing assertion. And owning sparsity IP does not, by itself, confer market share — it is a necessary tool in the cost fight, not a sufficient one. Patent counts and market position are different things, and conflating them is a classic analytical error.

The bottom line for a markets reader: in merchant AI silicon, the war is fought on cost-per-compute, and sparsity is one of the sharpest weapons. Intel's grant shows it is armed for that fight, down to the feedback-pipeline mechanics that make zero-skipping pay off. Whether the weapon wins customers is a commercial question the patent cannot settle — but the patent is where you confirm the strategy is real.