Disclosure or it didn't happen — and the disclosure here is a granted patent, not a slide. Long before “AI data center” became the line item that moves NVIDIA's stock, the company was filing on the unglamorous hardware that determines whether running a model is cheap or ruinous. The grant US10528864B2 (“Sparse convolutional neural network accelerator,” issued 2020-01-07) is one of those records.

Strip the title to its mechanism: many of the weights inside a trained neural network are zero, and multiplying by zero wastes silicon and power. The patent, classified in CPC G06N 3/063 (neural-network hardware), covers an accelerator that detects and skips those zeros so the chip spends its energy only on the math that matters. The named inventors include William J. Dally, NVIDIA's chief scientist — a signal of how central this work was treated internally.

“A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received.”— U.S. Patent No. 10,528,864 source

The claims spell out exactly how the zero-skipping works, and the elegance is in handling sparsity on both operands at once. Claim 1 receives a first vector "comprising only non-zero weight values and first associated positions … within a first space" and a second vector "comprising only non-zero input activation values and second associated positions" — the first space three-dimensional, the second two-dimensional. The hardware multiplies the non-zero weights by the non-zero activations "within a multiplier array" to produce a vector of products, then does the bookkeeping that makes sparsity work: it "combines the first associated positions with the second associated positions" — a vector addition of coordinates — "to produce a fourth vector of positions, wherein each position … is associated with a respective product." Because the array only ever holds non-zero values, it never wastes a cycle on a guaranteed-zero product; the position math is what lets it reassemble the answer in the right place afterward.

The output side is just as deliberate about not paying for zeros. The products are routed so that "each one … is transmitted to an adder in the accumulator array that is configured to generate an output activation value at the position associated with the product," and a dependent claim "compress[es] the output activation values to produce a set of vectors comprising … only the output activation values that are not equal to zero." Sparsity in, sparsity out — the chip keeps the data compact at every stage so the next layer inherits the savings. Another claim notes the second vector "was generated during processing of a first layer" and the products are "generated during processing of a second layer," which is how the technique chains across a deep network rather than helping in just one spot.

The design is built to scale across a large chip, too. The accelerator comprises "an array of processing elements, each processing element comprising a multiplier array," the weight vector "is broadcast to each processing element," and the activation space "is partitioned into two-dimensional tiles" so multiple multiplier arrays "generate additional products for the remaining two dimensional tiles" in parallel. Broadcast-and-tile is the language of a design meant to fill a wafer with parallel sparse-math units — the structural blueprint behind a high-throughput inference part.

The patent also covers the technique three ways — as a method, as a "convolutional neural network accelerator" comprising the processing-element array, and as a full "system" pairing that accelerator with "a non-transitory memory storing vectors comprising only non-zero weight values." Claiming the same invention at the method, chip, and system levels is how an assignee makes the IP hard to design around: a competitor cannot avoid it merely by moving the zero-detection logic from hardware into software or by repackaging the chip inside a different board. A further claim extends the tiling "for a number of input channels into an additional dimension," receiving separate non-zero weight vectors per channel — the detail that lets the same sparse-math scheme handle the multi-channel convolutions real vision and language workloads actually run.

The business point is that inference cost is the denominator under every AI gross-margin claim. A chip that does more useful work per watt is the difference between a profitable inference service and a subsidised one. NVIDIA does not break out a “sparse accelerator” revenue line, and no filing claims it does; what the patent establishes is that the cost advantage the company would later monetize was being engineered years ahead of the demand.

Read against the disclosures that came later, the through-line is clear. NVIDIA's Data Center segment, which its Form 10-K reports as the dominant revenue source today, sits on top of an architecture whose efficiency tricks were patented when that segment was a fraction of its current size. The 2020 grant is the receipt for a bet the income statement only validated afterward.

The caveat the house rule requires: a patent is a claim of invention, not a claim of revenue. We are not asserting this specific grant generates a disclosed dollar figure — it doesn't, and the filings don't say so. We are saying the IP behind the inference cost structure is real, dated, and assignee-attributed, with named mechanisms for skipping zeros on both weights and activations — which is more than most narratives about NVIDIA's “moat” can show.